(1) Field of the Invention
This invention relates to the passivation of exposed copper in a copper damascene structure and more specifically to dielectric layers used as an etch stop as well as passivation for exposed copper.
(2) Background of the Invention
As the cross section area of conductors in integrated circuits continue to shrink the conductivity of the conductor material becomes increasingly important. While aluminum has long been the conductor material of choice in integrated circuits, materials having greater conductivity such as gold, silver, copper, or the like are used with increasing frequency.
These metals have not had more widespread use because they suffer from a number of disadvantages such as the formation of undesirable intermetallics and high diffusion rates. Copper has the additional disadvantage of being easily oxidized at relatively low temperatures. One particular problem of this easy oxidation of copper is that conventional photoresist processing can not be used to pattern the copper. At the end of the patterning process using photoresist the photoresist must be removed by heating it in a highly oxidizing environment which also oxidizes the copper conductors. One solution to this problem is the Damascene process for forming copper conductors.
Although the damascene process for forming copper conductors avoids the use of photoresist to pattern the copper conductors, exposed copper remains after the patterning process. Passivation layers over the exposed copper are required to avoid oxidation of the exposed copper or contamination of the exposed copper during subsequent process steps or during wafer storage.
U.S. Pat. No. 5,744,376 to Chan et al. describes a method of forming copper interconnections using a damascene structure with provisions to prevent both copper diffusion and copper oxidation.
U.S. Pat. No. 5,693,563 to Teong describes a method of forming copper interconnections using an etch stop in a double damascene structure having provision to prevent both copper diffusion and oxidation.
U.S. Pat. No. 5,677,244 to Venkatraman describes damascene structure using a copper alloy as a conductor material.
U.S. Pat. No. 5,602,053 to Zheng et al. describes a method of forming a dual damascene structure using copper conductors and a pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene conductors.
Patent application Ser. No. 09/349,847, Filed Jul. 8, 1999, entitled xe2x80x9cMETHOD OF FABRICATING A DAMASCENE STRUCTURE FOR COPPER MEDULLIZATIONxe2x80x9d and assigned to the same Assignee describes a method of forming a copper damascene structure over a filled contact hole and the use of a sacrificial dielectric layer to protect an etch stop layer during chemical mechanical polishing.
Patent application Ser. No. 09/349,849, Filed Jul. 8, 1999, entitled xe2x80x9cROBUST POST Cu-CMP IMD PROCESSxe2x80x9d and assigned to the same Assignee describes methods of cleaning exposed copper between the steps of chemical mechanical polishing and intermetal dielectric deposition.
Forming damascene conductor structures using copper or other conducting materials requires the deposition of a layer of trench dielectric. A trench is then etched in the layer of trench dielectric to define the shape of the conductor. A layer of barrier metal is usually deposited over the trench dielectric, on the sidewalls of the trench, and on the bottom of the trench. A conductor metal, such as copper, is then deposited on the layer of barrier metal to more than fill the trench. The barrier metal and conductor metal are then removed down to the level of the trench dielectric, usually using a method such as chemical mechanical polishing, to define the conductor. This leaves exposed copper at the top of the conductor which is subject to contamination or oxidation and must be covered with a passivation layer.
Often the passivation layer must also function as an etch stop layer during subsequent processing, however materials which perform best as etch stop layers do not perform best as passivation layers. Silicon oxynitride, SiON, is usually preferred as a etch stop layer but is less desirable as a passivation layer because of delamination which can occur between copper and silicon oxynitride. Silicon nitride, SiN, avoids the delamination problem, and is a preferred passivation material, but is less desirable as an etch stop layer.
It is a principle objective of this invention to provide a method of forming a composite dielectric which performs well both as an etch stop and passivation layer.
It is another principle objective of this invention to provide a composite dielectric which performs well both as an etch stop and passivation layer.
These objectives are achieved by using a two material composite layer as a passivation layer. The first material, preferably silicon nitride, is chosen for its properties as a passivation layer and is deposited directly over the exposed copper. The second material, preferably silicon oxynitride, is chosen for its properties as an etch stop and is deposited directly over the first material. The composite layer can be thinner than a layer of the first material deposited thick enough to perform both as a passivation layer and an etch stop layer. A layer of inter-metal dielectric is then deposited over the composite layer and via holes can be formed in the inter-metal dielectric layer as needed.